preliminary 16-mbit (2m x 8) static ram cy7c1069dv33 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05478 rev. *c revised september 14, 2006 features ?high speed ?t aa = 10 ns ? low active power ?i cc = 125 ma @ 10 ns ? low cmos standby power ?i sb2 = 25 ma ? operating voltages of 3.3 0.3v ? 2.0v data retention ? automatic power-down when deselected ? ttl-compatible inputs and outputs ? easy memory expansion with ce 1 and ce 2 features ? available in pb-free 54-pin tsop ii package and 48-ball vfbga packages functional description the cy7c1069dv33 is a high-performance cmos static ram organized as 2,097,152 words by 8 bits. writing to the device is accomplished by enabling the chip (by taking ce 1 low and ce 2 high) and write enable (we ) inputs low. reading from the device is accomplished by enabling the chip (ce 1 low and ce 2 high) as well as forcing the output enable (oe ) low while forcing the write enable (we ) high. see the truth table at the back of this data sheet for a complete description of read and write modes. the input/output pins (i/o 0 through i/o 7 ) are placed in a high-impedance state when the device is deselected (ce 1 high or ce 2 low), the outputs are disabled (oe high), or during a write operation (ce 1 low, ce 2 high, and we low). the cy7c1069dv33 is available in a 54-pin tsop ii package with center power and ground (r evolutionary) pinout, and a 48-ball very fine-pitch ball grid array (vfbga) package. selection guide ?10 unit maximum access time 10 ns maximum operating current 125 ma maximum cmos standby current 25 ma logic block diagram pin configuration top view tsop ii we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 43 42 16 15 29 30 a 5 a 6 a 7 a 8 a 0 a 1 oe v ss a 17 i/o 7 a 2 ce 1 i/o 0 i/o 1 a 3 a 4 18 17 20 19 27 28 25 26 22 21 23 24 i/o 2 i/o 3 a 16 a 15 v cc i/o 6 nc i/o 5 i/o 4 a 14 a 13 a 12 a 11 a 9 a 10 ce 2 44 46 45 47 50 49 48 51 53 52 54 v ss v cc a 19 a 18 v cc v cc v ss nc v ss nc v cc v ss nc nc nc nc nc nc nc nc a 20 15 16 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer 2m x 8 array a 0 a 12 a 14 a 13 a a a 17 a 18 a 10 a 11 i/o 0 ?i/o 7 oe ce 2 we ce 1 a 9 a 19 a 20 [+] feedback [+] feedback
preliminary cy7c1069dv33 document #: 38-05478 rev. *c page 2 of 9 pin configurations [1] 48-ball vfbga we v cc a 11 a 10 a 6 a 0 a 3 ce 1 i/o 0 a 4 a 5 i/o 1 i/o 2 i/o 3 nc v ss a 9 a 8 oe v ss a 7 nc ce2 a17 a 2 a 1 v cc i/o 4 i/o 5 i/o 6 i/o 7 nc a 15 a 14 a 13 a 12 nc 3 2 6 5 4 1 d e b a c f g h (top view) a 16 a 19 a 20 nc nc nc nc a 18 nc nc nc note: 1. nc pins are not connected on the die [+] feedback [+] feedback
preliminary cy7c1069dv33 document #: 38-05478 rev. *c page 3 of 9 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc to relative gnd [2] .... ?0.5v to +4.6v dc voltage applied to outputs in high-z state [2] ....................................?0.5v to v cc + 0.5v dc input voltage [2] .................................?0.5v to v cc + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... .... ........... .............. ......>2001v (per mil-std-883, method 3015) latch-up current...................................................... >200 ma operating range range ambient temperature v cc industrial ?40 c to +85 c3.3v 0.3v dc electrical characteristics over the operating range parameter description test conditions ?10 unit min. max. v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage [2] ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 a i cc v cc operating supply current v cc = max., f = f max = 1/t rc, i out = 0 ma cmos levels 125 ma i sb1 automatic ce power-down current ?ttl inputs ce 2 < v il , max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 30 ma i sb2 automatic ce power-down current ?cmos inputs ce 2 < 0.3v, max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 25 ma capacitance [3] parameter description test conditions tsop ii vfbga unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 6 8 pf c out i/o capacitance 8 10 pf thermal resistance [3] parameter description test conditions all-packages unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four-layer printed circuit board tbd c/w jc thermal resistance (j unction to case) tbd c/w ac test loads and waveforms [4] notes: 2. v il (min.) = ?2.0v and v ih (max) = v cc + 2v for pulse durations of less than 20 ns. 3. tested initially and after any design or proc ess changes that may affect these parameters. 4. valid sram operation does not occur until the power supplies have reached the minimum operating v dd (3.0v). 100 s (t power ) after reaching the minimum operating v dd , normal sram operation can begin including reduction in v dd to the data retention (v ccdr , 2.0v) voltage. 90% 10% 3.0v gnd 90% 10% all input pulses 3.3v output 5 pf* *including jig and scope (a) (b) r1 317 ? r2 351 ? rise time > 1v/ns fall time: > 1v/ns (c) output 50 ? z 0 = 50 ? v th = 1.5v 30 pf* * capacitive load consists of all components of the test environment [+] feedback [+] feedback
preliminary cy7c1069dv33 document #: 38-05478 rev. *c page 4 of 9 ac switching characteristics over the operating range [5] parameter description ?10 unit min. max. read cycle t power v cc (typical) to the first access [6] 100 s t rc read cycle time 10 ns t aa address to data valid 10 ns t oha data hold from address change 3 ns t ace ce 1 low/ce 2 high to data valid 10 ns t doe oe low to data valid 5 ns t lzoe oe low to low-z [7] 1ns t hzoe oe high to high-z [7] 5ns t lzce ce 1 low/ce 2 high to low-z [7] 3ns t hzce ce 1 high/ce 2 low to high-z [7] 5ns t pu ce 1 low/ce 2 high to power-up [8] 0ns t pd ce 1 high/ce 2 low to power-down [8] 10 ns write cycle [9, 10] t wc write cycle time 10 ns t sce ce 1 low/ce 2 high to write end 7 ns t aw address set-up to write end 7 ns t ha address hold from write end 0 ns t sa address set-up to write start 0 ns t pwe we pulse width 7 ns t sd data set-up to write end 5.5 ns t hd data hold from write end 0 ns t lzwe we high to low-z [7] 3ns t hzwe we low to high-z [7] 5ns notes: 5. test conditions assume signal transition ti me of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v. test conditions for the read cycle use output loading shown in part a) of the ac test loads, unless specified otherwise. 6. t power gives the minimum amount of time that the power supply should be at typical v cc values until the first memory access can be performed. 7. t hzoe , t hzsce , t hzwe and t lzoe , t lzce , and t lzwe are specified with a load capacitance of 5 pf as in (b) of ac test loads. transition is measured 200 mv from steady-state voltage. 8. these parameters are guaranteed by design and are not tested. 9. the internal write time of the memory is defined by the overlap of ce 1 low/ce 2 high, and we low. ce 1 and we must be low along with ce 2 high to initiate a write, and the transition of any of these signals can terminate th e write. the input data set-up and hold timing should be refe renced to the leading edge of the signal that terminates the write. 10. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback [+] feedback
preliminary cy7c1069dv33 document #: 38-05478 rev. *c page 5 of 9 data retention characteristics (over the operating range) parameter description conditions min. typ. max. unit v dr v cc for data retention 2 v i ccdr data retention current v cc = 2v , ce 1 > v cc ? 0.2v, ce 2 < 0.2v, v in > v cc ? 0.2v or v in < 0.2v 25 ma t cdr [3] chip deselect to data retention time 0 ns t r [11] operation recovery time t rc ns data retention waveform switching waveforms read cycle no. 1 [12,13] read cycle no. 2(oe controlled) [13,14] notes: 11. full device operation requires linear v cc ramp from v dr to v cc(min.) > 50 s or stable at v cc(min.) > 50 s 12. device is continuously selected. ce 1 = v il , ce 2 = v ih . 13. we is high for read cycle. 14. address valid prior to or coincident with ce 1 transition low and ce 2 transition high. 3v 3v t cdr v dr > 2v data retention mode t r ce v cc previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t asce t doe t lzoe t lzsce t pu high impedance t hzoe t pd high oe ce 1 impedance address data out v cc supply t hzsce current i cc i sb ce 2 [+] feedback [+] feedback
preliminary cy7c1069dv33 document #: 38-05478 rev. *c page 6 of 9 write cycle no. 1(ce 1 controlled) [15,16,17] write cycle no.2(we controlled, oe low) [15,16,17] truth table ce 1 ce 2 oe we i/o 0 ?i/o 7 mode power h x x x high-z power-down standby (i sb ) x l x x high-z power-down standby (i sb ) l h l h data out read all bits active (i cc ) l h x l data in write all bits active (i cc ) l h h h high-z selected, outputs disabled active (i cc ) notes: 15. data i/o is high-impedance if oe = v ih . 16. if ce 1 goes high/ce 2 low simultaneously with we going high, the output remains in a high?impedance state. 17. ce above is defined as a combination of ce 1 and ce 2 . it is active low. switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw datai/o address ce we t oe low) t hd t sd t sce t ha t aw t pwe t wc data i/o address ce we t sa t lzwe t hzwe [+] feedback [+] feedback
preliminary cy7c1069dv33 document #: 38-05478 rev. *c page 7 of 9 ordering information speed (ns) ordering code package diagram package type operating range 10 CY7C1069DV33-10ZXI 51-85160 54-pin tsop ii (pb-free) industrial cy7c1069dv33-10bvxi 51-85178 48-ball ve ry fine pitch ball grid array (8 9.5 1 mm) (pb-free) package diagrams 51-85160-** 54-pin tsop type ii (51-85160) [+] feedback [+] feedback
preliminary cy7c1069dv33 document #: 38-05478 rev. *c page 8 of 9 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package diagrams a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25 m ?0.05 m b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.55 max. 0.25 c 0.10 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 8.000.10 9.500.10 a 9.500.10 8.000.10 b 1.875 2.625 0.26 max. c b a c b c d e f g h 12 3 45 6 a 48-ball fbga (8 x 9.5 x 1 mm) (51-85178) 51-85178. ** [+] feedback [+] feedback
preliminary cy7c1069dv33 document #: 38-05478 rev. *c page 9 of 9 document history page document title: cy7c1069dv33 16-mbit (2m x 8) static ram document number: 38-05478 rev. ecn no. issue date orig. of change description of change ** 201560 see ecn swi advance data sheet for c9 ipp *a 233748 see ecn rkf 1.ac, dc parameters are modified as per eros (spec # 01-2165) 2.pb-free offering in the ?ordering information *b 469420 see ecn nxr converted from ad vance information to preliminary removed ?8 and ?12 speed bins from product offering removed commercial operating range changed 2g ball of fbga and pin #40 of tsopii from dnu to nc included the maximum ratings for static discharge voltage and latch up current on page #3 changed i cc(max) from 220 ma to 100 ma changed i sb1(max) from 70 ma to 30 ma changed i sb2(max) from 40 ma to 25 ma specified the overshoot spec in footnote # 1 added data retention characteristics table on page #5 updated the 48-pin fbga package updated the ordering information table. *c 499604 see ecn nxr added note# 1 for nc pins updated test condition for i cc in dc electrical characteristics table updated the 48-ball fbga package [+] feedback [+] feedback
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